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FEATURES Fully Compliant with DECT Specifications Single IC DECT Radio Integrated UHF VCO (External Resonator) Integrated Synthesizer Supporting Extended Frequency Allocation Built-In Supply Regulation Direct VCO Modulation for DECT Transmit Path PLL-Based Demodulator Use with Low Cost Plastic Packaged SAW Filters Ultralow Power Design Operates from +3.0 V to +5.5 V Battery User-Selectable Power-Down Modes Small 48-Lead LQFP Package APPLICATIONS DECT Cordless Telephones DECT-Based Wireless Local Loop Systems DECT-Based Wireless Data Systems DESCRIPTION
DECT RF Transceiver AD6411
FUNCTIONAL BLOCK DIAGRAM
PLL DEMODULATOR LNA
RX DATA RSSI
PLL VCO PA
PFD
TX DATA
AD6411
CONTROL INTERFACE
The AD6411 provides the complete transmit and receive RF signal processing necessary to implement a digital wireless transceiver based on the Digital Enhanced Cordless Telecommunications (DECT) standard. The AD6411's receive signal path consists of a mixer, IF amplifiers and PLL demodulator. The low noise, high intercept mixer is a development of the doubly-balanced Gilbert-Cell type. It has a nominal -16 dBm input-referred 1 dB compression point and a -8 dBm input referred third-order intercept. The limiter amplifier provides sufficient gain to drive the PLL demodulator, which provides selectable analog or sliced outputs. The RSSI output provides a voltage proportional to the receive signal strength. It measures nearly 100 dB IF signal strength range with 14 mV/dB gain scaling.
The transmit path accepts baseband data, which is filtered and applied to the VCO directly. The VCO operates at half the RF carrier frequency, and is doubled to avoid pulling due to leakage from the output. An on-chip PLL frequency synthesizer provides channel selection. Operating modes are selected either through a serial bus or asynchronous control pins. This allows compatibility with most of the available DECT baseband controller ASICs. The AD6411 is packaged in a 48-lead LQFP.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD6411-SPECIFICATIONS (T = 25 C, 3.0 V < V
A
BAT <
5.5 V unless otherwise noted)
Min Typ 1880 to 1930 Max Units
Parameter RECEIVE RF MIXER RF Input Frequency
Conditions
MHz 21 dB dBm dBm dB 1.5:1 dB dBm dBm V V mV/dB 2 s A/rad pA MHz/V V/MHz dBc 1.44 100 +4 V A dBm dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz MHz kHz kHz k mV p-p MHz MHz mA mA nA V REV. 0
Power Gain Input 1 dB Compression Point Input Third-Order Intercept SSB Noise Figure Output VSWR Output Impedance Input Impedance RX IF AMPLIFIERS Differential Input Impedance Input VSWR IF Noise Figure RSSI RSSI Upper Limit RSSI Lower Limit RSSI High Level Voltage RSSI Low Level Voltage RSSI Slope RSSI Output Impedance RSSI Output Response Time PLL DEMODULATOR PLL Demodulator Phase Detector Gain Leakage Current at COFF Recommended External VCO Gain Demodulator Gain Demodulator Linearity VOLTAGE REFERENCE Output Voltage Output Current TRANSMIT SECTION Output Power Harmonically Related Spurii Other Spurii Output Phase Noise 1.2 MHz 3.0 MHz >4.7 MHz VCO Operating Frequency Range Oscillator Push Oscillator Pull SYNTHESIZER Reference Input Impedance Reference Input Level Reference Input Frequency VCO Signal Input Range Charge Pump Current - "Up" Charge Pump Current - "Down" Charge Pump Leakage BSW Output "High" Voltage
ZSOURCE = 50 , Z LOAD = 200 ZSOURCE = 50 , ZLOAD = 200 ZSOURCE = 50 , Z LOAD = 200 ZSOURCE = 50 , Z LOAD = 200 100 MHz-120 MHz
15 -21
19 -16 -8 11 200 50 200
1.5:1
Input Power < -11 dBm ZSOURCE = 200 Differential ZSOURCE = 200 Differential ZSOURCE = 200 Differential Input Power = 0 dBm (at IF Input) Input Power = -90 dBm (at IF Input) -90 dBm < Input Power < 0 dBm (at IF Input) VRSSI = 0.3 V Settling to 95% Value for a 40 dB Input Step, 20 pF External Load @ 90 Degree Relative Phase Charge Pump Disabled VCO Gain Set to 1.152 MHz/V THD for FM Tone @ 576 kHz, Peak Deviation 288 kHz 1.3 -5
6 +3 -95 1.7 0.3 14 700
80
115 100 1.152 1.736 -30 1.37
150
ZL = 50 At 0.5 x DECT_Tx: (940 MHz-950 MHz) At 1.5 x DECT_Tx: (2820 MHz-2850 MHz) 100 MHz-3000 MHz, Outside DECT Band 1 MHz Measurement Bandwidth With UHF Resonator Qu > 30
-3
+1 -10 -20 -73 -120 -130 -135
With Suitable External Resonator Using On-Chip Regulator, 250 mV VBAT Step Change with 5 s Rise/Fall Time VSWR = 2:1 Any Phase
700 6 55 >5 100 10 700 -1.30 0.66 2.5
1200
Voltage On Loop Filter (Pin 38) = 1.4 V Voltage On Loop Filter (Pin 38) = 1.4 V Output Disabled at ILOAD < = 2 mA -2-
1.0 1.0 < 1
1000 20 1200 -0.77 1.15
AD6411
Parameter VOLTAGE REGULATORS (VS1, VS2) Regulated Voltage Output Dropout Voltage Load Regulation Line Transient Response Line Rejection Power Supply Rejection POWER CONSUMPTION Supply Voltage All Off Mode Standby Mode Prior to TX Slot Active TX Slot Prior to RX Slot Active RX Slot OPERATING TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS 1
Conditions ILOAD = 60 mA max ILOAD = 60 mA; BCW68F or Equivalent Pass Transistor VS1: 10 mA < ILOAD < 60 mA VS2: 1 mA < ILOAD < 15 mA ILOAD = 10 mA , VBAT = 250 mV, Rise/Fall Time = 2 s ILOAD = 60 mA, VBAT = 250 mV, Static Change DC-1 MHz VBAT
Min 2.675
Typ 2.725 150
Max 2.825
Units V mV
20 1.5 0.5 35 3.0 100 <1 200 52 52 20 57 5.5 400 60 60 25 75 +85
mV mV mV dB V A A mA mA mA mA C
(Synthesizer Dividers On, Charge Pump Off)
15 45 -25
VCO VCCVCO
EN VBAT1
VCOB
DATA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 48-lead LQFP package: JA = +126C/W.
48 47 46 45 44 43 42 41 40 39 38 37
REF 1 SFS 2 DEMOD DATA 3 TX ENAB 4 COFF 5 DMR 6 IFLF 7 IFCP 8 IFVCO 9 VREF 10
GND LF
CLK
VCCPD
36 35 34 33 32
VF2 BSW
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . -25C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . .+300C
PIN CONFIGURATION 48-Lead LQFP (ST-48)
PIN 1 IDENTIFIER
GND VCCTX GND GND TXOP GND RX ENAB GND RFIN GND VCCRX GND
AD6411
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
ORDERING GUIDE Temperature Range Package Description Package Option ST-48
GND 11 VCCDM 12
13 14 15 16 17 18 19 20 21 22 23 24
Model
RSSI VCCIF2
VCCIF1
GND IFIN
VS1 VF1
SYN ENAB VBAT2
AD6411AST -25C to +85C 48-Lead Plastic LQFP
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6411 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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-3-
MXOP
IFINB GND
AD6411
PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11, 15, 18, 25, 27, 29, 31, 33, 34, 36, 39 12 13 14 16 17 19 20 21 22 23 24 26 28 30 32 35 37 38 40 41 42 43 44 45 46 47 48 Label REF SFS DEMOD_DATA TX_ENAB COFF DMR IFLF IFCP IFVCO VREF Description DECT Reference Clock Input S-Field Sample Demodulator Output OR Sliced Demodulator Output Transmit Section Power Control Input Demodulator Offset Capacitor Input for IF PLL Loop Filter Voltage after Data Filter Drive for IF PLL Active Loop Filter Virtual Ground for IF PLL Active Loop Filter External Resonator for Demodulator VCO Voltage Reference Output Type Input Input Output Input Output Input Output Input Input Output Comments HIGH = Sample; LOW = Hold Mode Controlled by DSD Bit in Control Register Active-High or Active-Low Set by TSB Bit in Setup Word Connect to External Capacitor
1.3 V; Can Be Used for A/D Converter Reference in Soft-Decision Applications
GND VCCDM RSSI VCCIF2 IFINB IFIN VCCIF1 VS1 VF1 SYN_ENAB VBAT2 MXOP VCCRX RFIN RX_ENAB TXOP VCCTX VCCPD LF VCOB VCCVCO VCO BSW VF2 VBAT1 EN DATA CLK
Ground PLL Demodulator Supply Receive Signal Strength Indicator Output IF Supply 2 IF Input IF Input IF Supply 1 Regulator Sense Regulator Force Synthesizer Section Power Control Input Connect to Battery Receive Mixer Output Receive RF Supply Receive Mixer Input Receive Section Power Control Input Transmit Output Transmit Supply Phase Detector and Charge Pump Supply Loop Filter (from Charge Pump Output) UHF Oscillator Supply for Second Regulator Sense UHF Oscillator Resonator Band Switch Output Regulator Force Connect to Battery 3-Wire Bus Enable 3-Wire Bus Data 3-Wire Bus Clock
Power Power Output Power Input Input Power Input Output Input Power Output Power Input Input Output Power Power Output Input Power Input Output Output Power Input Input Input
Normally Connected to VS1 Normally Connected to VS1 Balanced Input from IF SAW Filter Balanced Input from IF SAW Filter Normally Connected to VS1 Connect to Collector of VS1 Pass Device Connect to Base of VS1 Pass Device Active-High or Active-Low Set by SSB Bit in Setup Word
Normally Connected to VS1 Active-High or Active-Low Set by RSB Bit in Setup Word Open Collector Output Normally Connected to VS1 Normally Connected to VS1 VCO Tank Circuit Connect to Collector of VS2 Pass Device VCO Tank Circuit Controls Tank Circuit Band Segment Connect to Base of VS2 Pass Device
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AD6411
VCC L3 C2 TCI L2 VCC SAW C14 C13 + BPF1 LNA BPF2 + VCC L1 LOAD SYNTH REF DC RESTORE C6 C1 SFS R4 VREF 0...31 REFERENCE C7 BSW TXDATA REGULATOR #1 PFD C8 Q1 VBAT CONTROLLER INTERFACE 32/33 32/34 12/16 VBAT DMOD DATA R2 V1 R1 C3 C4 R3 L4 C5
S1 PA
X2
AD6411
REGULATOR #2
Q2
C9 R6 C11 R5 C10 DATA CLK EN RX ENAB SYN ENAB TX ENAB REF VBAT RSSI
C12
Figure 1. Functional Block Diagram
PRODUCT OVERVIEW
The AD6411 provides most of the active circuitry required to realize a complete low power DECT transceiver. Figure 1 shows the main sections of the AD6411. It consists, in the receive path, of a UHF mixer and two-stage IF strip with integrated demodulator and data slicer. The transmit path consists of a VCO, frequency doubler and buffer amplifier. Channel selection is performed by an on-chip PLL synthesizer. All AD6411 operating modes can be controlled by parallel control inputs or the serial interface.
Receive Mixer
The output of the mixer is single-ended. The nominal conversion gain is specified for operation into a 110.592 MHz or 112.32 MHz SAW IF DECT bandpass filter. The power gain of 17 dB is measured between the mixer input and the input of this filter.
IF Circuits and Demodulator
Demodulation is achieved via a PLL. This is shown in detail in Figure 2. An external manufacturing trim is required to achieve the required level of frequency accuracy. The approach is to adjust the capacitor TC1 (with the presence of an unmodulated carrier) such that the dc level at Pin 3 (DEMOD_DATA) is equal to the voltage on the external reference pin VREF. Two demodulation modes are supported. In one mode any frequency offset due to reference drift or frequency offsets on the incoming carrier are propagated to the output (referred to as "Normal" demodulation). The other method is to use a feature of the DECT system that enables a secondary compensation circuit to track out frequency offsets ("S-field sampling," which is enabled by the pin SFS--active high together with the configuration bit SFM set over the serial interface).
The UHF mixer is an improved Gilbert-cell design. The dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of -16 dBm in 50 at RFIN up to which the mixer remains linear and a valid RSSI signal is provided and, at the lower end, by the noise level. The local oscillator input of the receive mixer is internally provided by the LO, which is obtained by doubling the on-chip VCO frequency.
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-5-
AD6411
VCC 150nH 6.8pF 8pF ZC830 TC1 DMR VREF VREF GM3 DEMOD DATA SW3 1k DATA FILTER
AD6411
IFLF LOOP FILTER
SW1 IFVCO IFCP 96.768MHz GM1 SW2 IF/110.592MHz VARACTOR TEMP Co COMPENSATION 13.824MHz GM2 COFF
Figure 2. PLL Demodulator Block Diagram
The block diagram shows the principle of operation of these two modes together with the internal switch settings as shown in Figure 2.
Table I. Supported Demodulation Modes
UHF VCO
Mode
SW1
SW2
SW3
Comment
A single UHF VCO oscillator is provided operating at one-half the required frequency. Therefore, in transmit mode the oscillator operates from (approximately) 940 MHz to 950 MHz, and in receive mode the oscillator operates from (approximately) 884 MHz-895 MHz. This requires a switched resonator design, and band switch control is provided by the AD6411. A balanced oscillator configuration is used which has the advantages of rejection of common-mode interference and noise, and less coupling to and from other parts of the IC and radio.
Transmit Functions
Prior to RX Open Closed Closed Precharge Loop SFS = Don't Care Filter and C Offset SFM = 0 Capacitor Normal Demod - Open Closed Open Active RX SFS = Don't Care SFM = 0 S-Field Sample SFS = 1 SFM = 1 S-Field Hold SFS = 0 SFM = 1 Closed Open Open Use Temperature Compensated Reference Voltage
The DECT transmit function is achieved by direct modulation of the UHF VCO operating at half the final transmit output frequency. An on-chip doubler converts this to the final carrier frequency. In this mode the synthesizer is set to a high impedance mode i.e., "fly-wheeled." The drift is sufficiently low for both single-slot and double-slot transmit operation.
Synthesizer and LO Functions
Open Open Open
An important consideration in normal demodulation mode is any drift after the initial setup of the VCO. One mechanism is the Capacitance vs. Temperature coefficient of the external varactor. This has a known characteristic which is compensated by an internal reference voltage generation circuit.
A complete synthesizer is implemented on the IC that is capable of generating all the required DECT channel allocations (including the extended DECT bands). This synthesizer can use reference frequencies of either 13.824 MHz or 10.368 MHz, controlled by the RD bit in the control register.
Synthesizer Programming
The required channels are programmed by setting the RD bit in the control register to the correct value, then programming the A and M Counters as shown below through the serial interface.
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REV. 0
AD6411
Transmit
t
EN
HEN
t t
DHD
t
CLK
t
DECT Channel 9 8 7 6 5 4 3 2 1 0
DEN
DST
A Counter 1 2 3 4 5 6 7 8 9 10
M Counter 34 34 34 34 34 34 34 34 34 34
Frequency/MHz
CLK
1881.792 1883.520 1885.248 1886.976 1888.704 1890.432 1892.160 1893.888 1893.888 1897.344
DATA
MSB
LSB
Figure 3. Serial Interface Timing Diagram
Parameter Maximum Serial Clock Frequency Serial Data Set Up Time Serial Data Hold Time Enable Set Up to Clock High Clock Low to Enable Low
Symbol f_clk t_dst t_dhd t_hen t_den
Typ 13.824 8 8 10 5
Unit MHz ns ns ns ns
The A Counter range is 0-31, allowing the AD6411 to be used in the extended DECT bands, up to the following maximum frequency: A Counter 31 M Counter 34 Frequency/MHz 1933.632
The Least Significant Bit of the serial control word selects either the "one-time setup" register or the operating mode register, with the remaining 15 bits as data. Table II below details the internal IC register mapping.
Table II. Register Mapping
Receive (Local Oscillator Frequency)
Main values are shown for a 110.592 MHz IF frequency. Values in parentheses are for the 112.32 MHz. DECT Channel 9 8 7 6 5 4 3 2 1 0
Address (D0) 0 1
Function One-Time IC Setup IC Operating Mode
Comments See Table III See Table IV
A Counter 1 (0) 2 (1) 3 (2) 4 (3) 5 (4) 6 (5) 7 (6) 8 (7) 9 (8) 10 (9)
M Counter 32 32 32 32 32 32 32 32 32 32
Frequency/MHz 1771.200 1772.928 1774.656 1776.384 1778.112 1779.840 1781.568 1783.296 1785.024 1786.752 (1769.472) (1771.200) (1772.928) (1774.656) (1776.384) (1778.112) (1779.840) (1781.568) (1783.296) (1785.024)
AD6411 INITIAL SETUP
On power-up the state of the IC is not defined. A one-time setup register must be loaded through the serial interface port, and is selected when the LSB of the serial word is 0. After this onetime setup, a single serial word controls operation of the IC.
Table III. One-Time IC Setup Register D15 X D14 RSB D13 TSB D12 SSB D11 D10 D9 D8 BSWS
RXM1 RXM0 TXM
Serial Interface
The IC operating modes can be controlled via the 3-wire serial interface or via the three external control lines provided (TX_ENAB, RX_ENAB, SYN_ENAB). The three external control lines allow mode control of the IC if the baseband controller cannot access the serial interface between slots. In either case the 3-wire serial interface is used to program the channel number. Detailed below is the register setup and the serial interface operation. The serial interface consists of a 16-bit shift register and two registers for configuration of the IC and mode control. This allows mode control of the IC with a single 16-bit write. DATA is the serial data input (data MSB first), CLK is the shift register clock (positive edge trigger), EN (positive edge trigger) is the serial interface enable. All internal register values are retained when sections of the IC are powered down. Figure 3 shows the timing diagram for the serial interface.
D7 CF0
D6 CT1
D5 CT0
D4 DSD
D3 SFM
D2 PDS
D1 RD
D0 0
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-7-
AD6411
One-Time Setup Register Bit Definitions RSB: Receive Control Line Sense Bit CF0: Configuration Bit 0
CF0 0 1
Function Use Serial Interface for Mode Control Use External Control Lines for Mode Control
RSB 0 1
Function Receive Section POWER UP Active HIGH Receive Section POWER UP Active LOW
CT1, CT0: Charge Pump Test Bits
TSB: Transmit Control Line Sense Bit
CT1 0 0 1 1
CT0 0 1 0 1
Function Three-State Output Force Pump UP Current (Nom 1 mA) Force Pump DOWN Current (Nom 1 mA) Normal Operation (Driven from PFD)
TSB 0 1
Function Transmit Section POWER UP Active HIGH Transmit Section POWER UP Active LOW
SSB: Synthesizer Control Line Sense Bit
DSD: Disable Data Slicer
SSB 0 1
Function Synthesizer POWER UP Active LOW Synthesizer POWER UP Active HIGH
DSD 0 1
Function Disable On-Chip Data Slicer. Analog Output at Pin DEMOD_DATA Enable On-Chip Data Slicer. Digital Output at Pin DEMOD_DATA
RXM1, RXM0: Divider Power Mode In Active Receive Slot
RXM1 0 0 1 1
RXM0 0 1 0 1
Function Dividers Powered Down, VCO Flywheeled in Active Receive Mode Dividers Powered Up, VCO Flywheeled in Active Receive Mode Dividers Powered Up, VCO Locked to Synthesizer in Active Receive Mode Dividers Powered Up, VCO Locked to Synthesizer in Active Receive Mode
DSD bit is configured at power-up depending on whether an external data slicer is being used in the system. Data slicer is disabled when the IF strip is powered down irrespective of the status of bit DSD.
SFM: S-Field Mode
SFM 0 1
Function Normal Demodulation Mode S-Field Sampling Mode
PDS: Phase Detector Sense
TXM: Divider Power Mode In Active Transmit Slot
PDS 0 1
Function PFD Pumps UP when Fvco > Fref PFD Pumps UP when Fref > Fvco
TXM 0 1
Function Dividers Powered Down, VCO Flywheeled in Active Mode Dividers Powered Up, VCO Flywheeled in Active Mode
RD: Reference Divide Ratio
RD 0 1
Function Reference Frequency = 10.368 MHz Reference Frequency = 13.824 MHz
BSWS: Band Switch Sense (Control with External Lines)
BSWS 0 1
Function Band Switch Output High in Receive Slot, PIN Diode ON Band Switch Output Low in Receive Slot, PIN Diode ON
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AD6411
CONTROLLING THE AD6411 OPERATING MODE Table IV. Operating Mode Control Register D15 M0 D14 A4 D13 A3 D12 A2 D11 A1 D10 A0 D9 D8 CHANNEL SELECTION/FREQUENCY CONTROL
The M0 and A4-A0 bits in the operating mode register control the channel selection for the AD6411 synthesizer. The M0 bit selects the M Counter division ratio.
M0: M Counter Divide Ratio
IF/RSSI RXMixer
M0 0 1
Function M Divide Ratio 32 M Divide Ratio 34
D7 DMOD
D6 DIV
D5 CP
D4 TX BUF
D3 UHF VCO
D2 BSW
D1 REGS
D0 1
The operating mode register, loaded through the serial port when the LSB is "1," allows any circuit block to be independently powered on or off. This can be bypassed to enable mode control of the IC via the three external control lines. Transitions between major DECT modes can be made with a single word program (including channel change) when using the serial interface only. Table V defines the bit status for the various IC operating modes when used with the serial interface only.
Table V. Bit Status for the Different Operating Modes
The A4 through A0 bits control the A counter division ratio, and control the channel selection. Refer to the section of this data sheet on Synthesizer Programming for a mapping of channel frequency to synthesizer divider words.
A4-A0: A Counter Division Ratio
"A" 0 1 2 3 - 30 31
A4 0 0 0 0 - 1 1
A3 0 0 0 0 - 1 1
A2 0 0 0 0 - 1 1
A1 0 0 1 1 - 1 1
A0 0 1 0 1 - 0 1
Data Bits (D9 . . . D0) Operating Mode Register 00 0000 0101 00 0000 0111 00 0111 1111
Function All Off Mode Stand-By Mode Prior to TX Slot
Comments All Circuits Off Regulators On VCO, TX Buffer, Dividers, Charge Pump, Regulators Active, VREF (1.4 V) Active VCO, TX Buffer, Dividers, Regulator Circuits Active, VREF (1.4 V) Active1 VCO2, Dividers, Charge Pump, Regulators, Demodulator Precharge Circuits Active, VREF (1.4 V) Active RX Mixer, VCO2, Dividers, Regulators, Demodulator, Receive Strip Circuits Active, VREF (1.4 V) Active
ANALOG/RF INTERFACE DETAILS
The AD6411 is an advanced 1.9 GHz radio transceiver circuit and requires careful attention to the selection of external components. The AD6411 is readily capable of performance that meets the ETS-300-176-1 (formerly TBR06) DECT radio specifications. This section of the data sheet will describe suggestions for external componentry that will allow the design of a complete DECT RF transceiver.
Low Noise Amplifier
00 0101 1111
Active TX Slot
00 1110 1011
Prior to RX Slot
An external LNA is required to meet the RF leakage specifications in ETS-300-176-1. The following circuit, based on a Siemens BFP405 discrete transistor, is representative of a suitable LNA. The SC1.89 SAW filter removes images prior to the down converter. The filter is matched to the AD6411 input with a printed inductor and fixed capacitor. Complete details of the circuit, with transmission-line dimensions, can be found in Siemens Application Note No. 020.
100pF +3V 10nF 100 33pF
11 1100 1011
Active RX Slot
33pF
39k
TL6 TL5 RF OUT 10 TL4 10pF
NOTES 1 Alternatively it may be possible to power-down the dividers in an active transmit slot depending on the effect of thermal transients on VCO pulling. In this mode the dividers are biased but inactive. This can also be implemented when external control lines are used with bits TXM, RXM1, RXM0. 2 Band switch output is determined by the status of BSW. Band switch output is Low when BSW is high, high when BSW is low. In Table V, band switch output is high for AcRx and PrRx slots, otherwise it is low.
TL1 22pF RF IN TL2 TL3
BFP405
Figure 4. LNA circuit
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-9-
AD6411
UHF VCO Tank Circuit
The UHF VCO is probably the most critical part of an AD6411based DECT radio. The design shown in Figure 5 uses a printed inductor, a BBY53 (or equivalent) common-cathode dual varactor, and a PIN-diode (BAR63-03W or equivalent) band switch to cover the DECT band. The capacitance added to the tank circuit by the PIN-diode is needed to switch the VCO to the DECT receive band. It is switched out of the circuit in the transmit mode, in which the VCO is directly modulated by baseband transmit data. With this scheme, no manufacturing trim is needed to tune the VCO to the DECT band. Tank component values will need slight modification to cover the "extended DECT" frequency bands. The dimensions of tank inductor L1 will depend on the circuit board material and thickness used. Contact Analog Devices for assistance on UHF tank inductor layout.
AD6411
10nF
VBAT
REGULATOR #1 10nF VBAT 10nF 10pF TO PIN 40 (VCOB) 1nF
REGULATOR #2
PASS TRANSISTORS: BCW68F OR EQUIVALENT
Figure 6. Voltage Regulator Circuitry
Transmit/Receive Switching
VCCVCO VCOB 2k BSW BAR63-03W
Since the same antenna is used for both transmit and receive, a switch consisting of PIN diodes and printed transmission lines is used to disconnect the receive path from the antenna during transmit periods. A suggested circuit is shown in Figure 7. Complete details can be found in Siemens Application Note No. 007.
2pF ANT
AD6411
VCO
2k
2pF 1.2pF 8.2pF L1 BAR80
8.2pF 20k 20k
TX DATA IN
BAR63-03W FROM PA 27nH
50 /4 BAR80 TO RX IN
10k 10k
10k
LF 6.8k 1nF
47pF 330pF 6.8pF 470pF
Figure 5. UHF VCO Circuit
Power Management
TX/RX 1=TX 0=RX
The AD6411 reduces the external components needed for power management in a DECT radio by integrating voltage regulators on-chip. The circuit can therefore operate directly from a 3.0 V to 5.5 V unregulated battery supply. There are two regulators. The first, VS1 (Pins 20, 21 and 23), uses an external BCW68F (or similar) PNP pass transistor to provide a regulated 2.75 V nominal supply voltage to most of the AD6411 circuitry. The second regulator, VS2 (Pins 41, 44, and 45), is intended to provide the regulated voltage to the UHF VCO section and should not be used for other circuitry.
Figure 7. T/R Switch
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REV. 0
AD6411
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Plastic LQFP (ST-48)
0.362 (9.2) SQ 0.346 (8.8) 0.280 (7.10) SQ 0.272 (6.90)
48 1 37 36
0.063 (1.60) MAX 0.020 (0.52) 0.019 (0.48) SEATING PLANE
TOP VIEW
(PINS DOWN)
0.217 (5.50) BSC SQ
25 24
0.006 (0.15) 0.002 (0.05)
12 13
0.006 (0.15) MAX 0.057 (1.45) 0.053 (1.35) 0.0197 (0.50) TYP 0.011 (0.27) 0.006 (0.17)
D
REV. 0
-11-
PRINTED IN U.S.A.
C3405-2.5-9/98

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